DS1013 3-in-1 silicon delay line DS1013 021798 1/5 features ? all-silicon time delay ? 3 independent buffered delays ? delay tolerance 2ns for -10 through -60 ? stable and precise over temperature and voltage range ? leading and trailing edge accuracy ? economical ? auto-insertable, low profile ? standard 14-pin dip, 8-pin dip, or 16-pin soic ? low-power cmos ? ttl/cmos-compatible ? vapor phase, ir and wave solderable ? custom delays available ? quick turn prototypes ? extended temperature ranges available pin assignment in 1 nc in 2 nc in 3 nc gnd vcc nc out 1 nc out 2 nc out 3 in 1 in 2 in 3 gnd vcc out 1 out 2 out 3 in 1 nc nc in 2 nc in 3 nc gnd nc nc out 1 nc out 2 nc out 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1 2 3 4 8 7 6 5 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 DS1013s 16-pin soic (300 mil) see mech. drawings section DS1013m 8-pin dip (300 mil) see mech. drawings section DS1013 14-pin dip (300 mil) see mech. drawings section v cc pin description in 1, in 2, in 3 inputs out 1, out 2, out 3 outputs gnd ground v cc +5 volts nc no connection description the DS1013 series of delay lines has three independent logic buffered delays in a single package. the devices are offered in a standard 14-pin dip which is pin-com- patible with hybrid delay lines. alternative 8-pin dip and surface mount packages are available which save pc board area. since the DS1013 products are an all sili- con solution, better economy is achieved when com- pared to older methods using hybrid techniques. the DS1013 series delay lines provide a nominal accuracy of 2ns for delay times ranging from 10 ns to 60 ns, in- creasing to 5% for delays of 150 ns and longer. the DS1013 delay line reproduces the input logic state at the output after a fixed delay as specified by the dash number extension of the part number. the DS1013 is designed to reproduce both leading and trailing edges with equal precision. each output is capable of driving up to ten 74ls loads. dallas semiconductor can cus- tomize standard products to meet special needs. for special requests and rapid delivery, call (972) 3714348.
DS1013 021798 2/5 logic diagram figure 1 in 1 out 1 td in 2 out 2 td in 3 out 3 td part number delay table (t phl , t plh ,) table 1 part no. delay per output (ns) DS1013-10 10/10/10 DS1013-12 12/12/12 DS1013-15 15/15/15 DS1013-20 20/20/20 DS1013-25 25/25/25 DS1013-30 30/30/30 DS1013-35 35/35/35 DS1013-40 40/40/40 DS1013-45 45/45/45 DS1013-50 50/50/50 DS1013-60 60/60/60 DS1013-70* 70/70/70 DS1013-75* 75/75/75 DS1013-80* 80/80/80 DS1013-100* 100/100/100 DS1013-150** 150/150/150 DS1013200** 200/200/200 custom delays available. * 3% tolerance. ** 5% tolerance.
DS1013 021798 3/5 timing diagram: silicon delay line figure 2 1.5v 1.5v 1.5v 1.5v 1.5v in t fall t rise 80% 20% t plh t phl out t wi t wi period test circuit figure 3 pulse td time start stop d.u.t z 0 = 50 w generator interval counter
DS1013 021798 4/5 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0 c to 70 c;v cc = 5.0v 5%) parameter symbol test cond. min typ max units notes supply voltage v cc 4.75 5.00 5.25 v 1 high level input voltage v ih 2.2 v cc +0.5 low level input voltage v il -0.5 0.8 v 1 input leakage current i i 0.0v < vi < v cc -1.0 1.0 m a active current i cc v cc = max period= min. 40 70 ma 2 high level output current i oh v cc = min. v oh = 4.0v -1.0 ma low level output current i ol v cc =min v ol =0.5v 12.0 ma ac electrical characteristics (t a = 25 c; v cc = 5.0v 5%) parameter symbol min typ max units notes input pulse width t wi 100% of t plh ns input to output delay (leading edge) t plh table 1 ns 3,4,5,6 input to output delay (trailing edge) t phl table 1 ns 3,4,5,6 power-up time t pu 100 ms period 3(t wi ) ns 7 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf
DS1013 021798 5/5 notes: 1. all voltages are referenced to ground. 2. measured with outputs open. 3. v cc = 5v @ 25 c. delays accurate on both rising and falling edges within 2 ns for -10 to -60, 3% for -70 to -100 and 5% for -150 and longer delays. 4. see atest conditionso section. 5. the combination of temperature variations from 25 c to 0 c or 25 c to 70 c and voltage variations from 5.0v to 4.75v or 5.0v to 5.25v may produce an additional delay shift of 1.5 ns or 3%, whichever is greater. 6. all output delays tend to vary unidirectionally over temperature or voltage ranges (i.e., if out 1 slows down, all other outputs also slow down). 7. period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling, layout, etc.). terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse be- tween the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of the corresponding output pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of the corresponding output pulse. test setup description figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1013. the input waveform is produced by a precision pulse gener- ator under software control. time delays are measured by a time interval counter (20 ps resolution) connected between each input and corresponding output. each output is selected and connected to the counter by a vhf switch control unit. all measurements are fully au- tomated, with each instrument controlled by a central computer over an ieee 488 bus. test conditions input: ambient temperature: 25 c 3 c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ohms max. rise and fall time: 3.0 ns max. pulse width: 500 ns period: 1 m s output: each output is loaded with the equivalent of one 74f04 input gate. delay is measured at the 1.5v level on the rising and falling edge. note: above conditions are for test only and do not restrict the operation of the device under other data sheet condi- tions.
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